Design a Full Adder Using 4 1 Mux

What is a mux or multiplexer ?

A multiplexer or mux in short, is a digital element that transfers data from one of the N inputs to the output based on the select signal. The case shown below is when N equals 4. For example, a 4 bit multiplexer would have N inputs each of 4 bits where each input can be transferred to the output by the use of a select signal.

sel is a 2-bit input and can have four values. Each value on the select line will allow one of the inputs to be sent to output pin out.

          sel     a     b     c     d     out 	 0          3          7     1     9          3          1      3          7          1     9          7          2      3     7          1          9          1          3      3     7     1          9          9        

A 4x1 multiplexer can be implemented in multiple ways and here you'll see two of the most common ways:

• Using an assign statement
• Using a case statement

Using assign statement

                      module mux_4to1_assign ( input [3:0] a,                 // 4-bit input called a                          input [3:0] b,                 // 4-bit input called b                          input [3:0] c,                 // 4-bit input called c                          input [3:0] d,                 // 4-bit input called d                          input [1:0] sel,               // input sel used to select between a,b,c,d                          output [3:0] out);             // 4-bit output based on input sel     // When sel[1] is 0, (sel[0]? b:a) is selected and when sel[1] is 1, (sel[0] ? d:c) is taken    // When sel[0] is 0, a is sent to output, else b and when sel[0] is 0, c is sent to output, else d    assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);      endmodule                  

The module called mux_4x1_assign has four 4-bit data inputs, one 2-bit select input and one 4-bit data output. The multiplexer will select either a , b, c, or d based on the select signal sel using the assign statement.

Using case statement

Note that the signal out is declared as a reg type because it is used in a procedural block like always.

                      module mux_4to1_case ( input [3:0] a,                 // 4-bit input called a                        input [3:0] b,                 // 4-bit input called b                        input [3:0] c,                 // 4-bit input called c                        input [3:0] d,                 // 4-bit input called d                        input [1:0] sel,               // input sel used to select between a,b,c,d                        output reg [3:0] out);         // 4-bit output based on input sel                       // This always block gets executed whenever a/b/c/d/sel changes value    // When that happens, based on value in sel, output is assigned to either a/b/c/d    always @ (a or b or c or d or sel) begin       case (sel)          2'b00 : out <= a;          2'b01 : out <= b;          2'b10 : out <= c;          2'b11 : out <= d;       endcase    end endmodule                  

The module called mux_4x1_case has four 4-bit data inputs, one 2-bit select input and one 4-bit data output. The multiplexer will select either a , b, c, or d based on the select signal sel using the case statement.

Hardware Schematic

Both types of multiplexer models get synthesized into the same hardware as shown in the image below.

Testbench

                      module tb_4to1_mux;     // Declare internal reg variables to drive design inputs    // Declare wire signals to collect design output    // Declare other internal variables used in testbench    reg [3:0] a;    reg [3:0] b;    reg [3:0] c;    reg [3:0] d;    wire [3:0] out;    reg [1:0] sel;    integer i;        // Instantiate one of the designs, in this case, we have used the design with case statement    // Connect testbench variables declared above with those in the design    mux_4to1_case  mux0 (   .a (a),                            .b (b),                            .c (c),                            .d (d),                            .sel (sel),                            .out (out));     // This initial block is the stimulus    initial begin       // Launch a monitor in background to display values to log whenever a/b/c/d/sel/out changes       $monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h out=0x%0h", $time, sel, a, b, c, d, out);        	  // 1. At time 0, drive random values to a/b/c/d and keep sel = 0       sel <= 0;       a <= $random;       b <= $random;       c <= $random;       d <= $random;              // 2. Change the value of sel after every 5ns       for (i = 1; i < 4; i=i+1) begin          #5 sel <= i;       end              // 3. After Step2 is over, wait for 5ns and finish simulation       #5 $finish;    end endmodule                  

Simulation Log

ncsim> run [0] sel=0x0          a=0x4          b=0x1 c=0x9 d=0x3          out=0x4          [5] sel=0x1 a=0x4          b=0x1          c=0x9 d=0x3          out=0x1          [10] sel=0x2 a=0x4 b=0x1          c=0x9          d=0x3          out=0x9          [15] sel=0x3 a=0x4 b=0x1 c=0x9          d=0x3          out=0x3          Simulation complete via $finish(1) at time 20 NS + 0        

Design a Full Adder Using 4 1 Mux

Source: https://www.chipverify.com/verilog/verilog-4to1-mux

Share this post